Patents Summary

Single Stack implementation of a Reed-Solomon encoder/decoder

Patent Number 5,396,502

The present invention is for a Error Correction Unit (ECU) that uses a single stack architecture for the generation, reduction and evaluation of the polynomials involved in the correction of a Reed-Solomon code. The circuit uses the same hardware to generate the syndromes, reduce the .OMEGA.(x) and .LAMBDA.(x) polynomials and evaluate the .OMEGA.(x) and .LAMBDA.(x) polynomials. Some of the specifics involved in calculating and reducing the polynomials mentioned above are novel as well. First, the implementation of the general Galois field multiplier is new and faster than previous implementations. Second, the circuit for implementing the Galois field inverse function has not appeared in prior art designs. Third, a novel method of generating the .OMEGA.(x) and .LAMBDA.(x) polynomials (including alignment of these polynomials prior to evaluation) is utilized. Fourth, corrections are performed in the same order as they are received using a premultiplication step prior to evaluation. Fifth, a novel method of implementing flags for uncorrectable errors is used. Sixth, the ECU is data driven in that nothing happens if no data is present. Finally, interleaved data is handled internally to the chip.

Adaptive data compression system with systolic string matching logic

Patent Number 5,532,693

An adaptive lossless data compression system with systolic string matching logic performs compression and decompression at the maximum rate of one symbol per clock cycle. The adaptive data compression system uses an improvement of the LZ1 algorithm. A content addressable memory (CAM) is used to store the last n input symbols. The CAM is stationary, stored data is not shifted throughout the CAM, but rather the CAM is used as a circular queue controlled by a Write Address Pointer Counter (WREN). During a compression operation, a new input symbol may be written to the CAM on each clock cycle, while simultaneously the rest of the CAM is searched for the input symbol. Associated with each word of the CAM array is a String Match State Machine (SMSM) and, an address logic module (ALM). These modules detect the occurrence of strings stored in the CAM array that match the current input string and report the address of the longest matching string nearest to the Write Address Pointer. The SMSM modules constitute a systolic logic array, where state information is shifted synchronously in the direction of the Write Address Pointer. The strings are represented by a string code which includes a length value, representing the length of the string, and a position value, representing the position in the CAM of the beginning of the string. During a decompression operation, the single symbols and string codes are input to the system. The symbols are stored in the CAM and the control logic outputs the decompressed data symbols using the stored data and the string codes.

Radio Frequency (RF) Converter System with Distributed Protection Switching and Method therefor

Patent Number 5,666,646

The present invention relates to an improved RF converting system. The RF converting system is comprised of a plurality of RF converter modules which are configured for redundant system operation using distributed protection switching in an active “daisy chain” configuration. The “daisy chain” configuration distributes the converter protection switching functions to each individual RF converter module through a switching module coupled to each of the RF converter modules. The “daisy chain” terminates in a backup RF converter which assumes the frequency and attenuation of a faulted RF converter module. A high speed bus provides communication interface between each of the online RF converter modules and the backup RF converter module so that the backup RF converter module can detect faults and reconfigure the system to replace a failed RF converter module. When a fault is detected on an RF converter module, the faulted RF converter module can be detached from the active RF converting system by separating the RF converter module from its switch module leaving the active online RF converting system intact through the switch module. The distributed protection switching in an active “daisy chain” configuration may also be used to provide reliable backup protection for other types of communication equipment.

Apparatus and method for increased data access in a network file oriented caching system

Patent Number 5,682,514

An apparatus for increased data access in a file oriented network comprises a file server computer having an operating system, a first memory, a permanent storage memory and a processor, a cache verifying computer operably connected to the file sever computer in a manner to form a network for rapidly transferring data, the cache verifying computer having an operating system, a first memory and a processor with means for performing an operation on data stored in the permanent storage memory of the file server computer to produce a signature of the data, a remote client computer having an operating system, a first memory, a cache memory and a processor with means for performing an operation on data stored in the cache memory to produce a signature of the data, a communication server operably connecting to the remote client computer to the cache verifying computer and the file sever computer, and a comparator operably associated with the cache verifying computer for comparing the signatures of data with one another to determine whether the signature of data of the remote client is valid.

Sliding Window with big gap data compression system

Patent Number 5,694,125

A sliding window with big gap data compression system is simple to implement and gives good compression over a wide variety of bilevel images. A sliding window compressor with a very small window size is utilized in conjunction with a storage buffer which is large enough to hold at least an entire scan line of data symbols. Coupled to the storage buffer is circuitry that checks for a match between the incoming data symbol and a symbol stored in one specific programmable location. This programmable location is preferably exactly one scan line length away. Match locations are either within the range of the small window or exactly equal to the specific programmable location. The entire compressor can be viewed as a sliding window with a big gap (SWBG). This sliding window is of a length corresponding to the length of the scan line, comprised of the small window followed by a big gap and then the one specific programmable location, at the end of the scan line.

Multiport RAM for use with a Viterbi decoder

Patent Number 5,822,341

A memory block structure for use within a viterbi decoder includes multiple dual port RAMs configured as multiport RAMs. The memory block structure is configured to allow a one-word write operation and an N-word read operation during a single clock cycle in order to achieve one decoded output symbol per clock period using the viterbi algorithm. By using dual port RAMs, a more densely packed and less expensive memory block structure is achieved. An encoded stream of input symbols are input to the viterbi decoder and written to the memory block structure one word at a time. Once X+Y bits have been written to the memory block structure, the decoder will then read N words from the memory block structure, simultaneously, reading back through X+Y words and outputting Y bits N at a time at the end of the trace back through memory. This process is repeated once the next Y words have been written to the memory block 22, with X+Y words being traced back through and the appropriate Y bits being output, until the entire encoded stream of input symbols has been decoded.

Apparatus and Method for Increased Data Access in a Network File Oriented Caching System

Patent Number 5,835,943

An apparatus for increased data access in a network includes a file server computer having a permanent storage memory, a cache verifying computer operably connected to the file server computer in a manner to form a network for rapidly transferring data, the cache verifying computer having an operating system, a first memory and a processor with means for performing an operation on data stored in the permanent storage memory of the file server computer to produce a signature of the data characteristic of one of a file and directory, a remote client computer having an operating system, a first memory, a cache memory and a processor with means for performing an operation on data stored in the cache memory to produce a signature of the data, a communication server operably connected to the remote client computer to the cache verifying computer and the file server computer and comparators operably associated with the cache verifying computer and remote client computer for comparing the signatures of data with one another to determine whether the signature of data of the remote client is valid.

Apparatus and Method for Increased Data Access in a Network File Object Oriented Caching System

Patent Number 6,012,085

An apparatus for increased data access in a network includes a file/object server computer having a permanent storage memory, a cache verifying computer operably connected to the file/object server computer in a manner to form a network for rapidly transferring data, the cache verifying computer having an operating system, a first memory and a processor capable of performing an operation on data stored in the permanent storage memory of the file/object server computer to produce a signature of the data characteristic of one of a file, an object and a directory, a remote client computer having an operating system, a first memory, a cache memory and a processor capable of performing an operation on data stored in the cache memory to produce a signature of the data, a communication server operably connected to the remote client computer to the cache verifying computer and the file/object server computer and comparators operably associated with the cache verifying computer and remote client computer for comparing the signatures of data with one another to determine whether the signature of data of the remote client is valid.

Hybrid Analog-Digital Phase Lock Loop Multi-frequency Synthesizer

Patent Number 6,028,460

A hybrid multi-frequency synthesizer is comprised of an analog phase lock loop, a digital phase lock loop and a phase lock loop monitor. The digital phase lock loop provides an accelerated, accurate frequency acquisition mode for the synthesizer. The analog phase lock loop provides a robust operating mode after frequency acquisition is achieved. The phase lock loop monitor provides a control circuit that monitors the synthesizer for frequency and phase perturbations. The phase lock loop monitor controls an electronic switch that selects either the analog or digital phase lock loop. The invention is further characterized by programmable band pass filtering, peak sensitivity detection and a fast lock feature.

Apparatus and Method for Increased Data Access in an Object Oriented Caching System

Patent Number 6,122,637

An apparatus having an object server computer having an operating system, a first memory, a permanent storage memory and a processor with a module for performing an operation on a predetermined object data stored in the permanent storage memory of the object server computer to produce an object server computer signature of the predetermined object data and a remote client computer operably associated with the object server computer having an operating system, a first memory, a cache memory and a processor with a module for performing an operation on like predetermined object data stored in the cache memory and recalling signature of the like predetermined object data, and a comparator operably associated with the remote client computer for comparing the signature of the predetermined object data with signature of the like predetermined object data to determine whether the signature of the like predetermined object data is valid.

Apparatus and Method for Increasing Speed in a Network File/Object Oriented Server/Client System

Patent Number 6,339,787

An apparatus for increased data access from data of the type including at least one of a file, an object and a directory in a file/object oriented network comprises a file/object server computer having an operating system, a first memory, a permanent storage memory, and a processor, a remote client computer operably connected to the file/object server computer in a manner to rapidly transfer data objects, having an operating system, a first memory, a permanent storage memory, and a processor, a communication link operably connecting the remote client computer and the file/object server computer including a router for routing between a WAN and a LAN, software operably associated with one of the file/object server computer and the remote client computer for determining whether data objects are transferred through the WAN or the LAN, software operably associated with one of the file/object server computer and the remote client computer for compressing the data objects upon detecting transfer through the WAN, and software for assembling the data objects into a stream and transferring the data objects through one of the WAN and the LAN.

Turbo product code decoder

Patent Number 6,526,538

The present invention is a turbo product code decoder capable of decoding multi-dimensional coding schemes. The decoder may be implemented in any digital communication system capable of receiving an encoded stream of data. The decoder is configured for receiving soft decision values. The decoder iteratively decodes the data by generating new soft difference values for each axis-iteration of decoding. These soft difference values represent the change in soft decision values after each axis-iteration. The soft difference values from each axis-iteration are then summed with the original soft decision values in decoding each of the other axis. After any full iteration–i.e. after all axis dimensions have been decoded one full time, the previous difference values for any axis are discarded when that axis is decoded in subsequent iterations. Accordingly, the same information is not continuously fed into the decoder during each subsequent iteration, thereby decreasing the likelihood of error and offering an improvement over prior decoders. Moreover, using unique nearest neighbor computation logic, the decoder of the present invention is able to generate valid nearest neighbors more efficiently without requiring the use of a look-up table, thereby reducing the amount of time required to decode. Finally, the decoder of the present invention utilizes four decoders arranged in parallel along with a unique memory array accessing scheme such that multiple rows or columns may be decoded at the same time, thereby increasing the data throughput time of the decoder over prior turbo product code decoders.

System for Increasing Data Access in Network having Compression Device for Determining and Controlling Data/Object Compression based on Predetermined Maximum Percentage of CPU Processing Capacity

Patent Number 6,615,275

An apparatus for increased data access from data of the type including at least one of a file, an object and a directory in a file/object oriented network comprises a compression device having means for determining when processing said CPU reaches a predetermined percentage of maximum processing capacity, and means operably associated with said determining means for controlling compression of data/object upon reaching said predetermined percentage in a manner to aid processing to fall below said predetermined percentage.

Digital Summing Phase-Lock Loop Circuit with Sideband Control and Method therefor

Patent Number 6,753,711

A digital summing phase-lock loop circuit with sideband control provides high accuracy and high speed acquisition in a multi-loop frequency synthesizer. A digital phase comparator is used to control a voltage-controlled oscillator in response to inputs from multiple external loops. An initial sweep condition is set by a sweep control circuit to provide resolution of lock ambiguities in the multiple external loops. Sideband selection may be performed by selecting on of an inverted or non-inverted output of the digital phase comparator.

Turbo product code decoder

Patent Number 6,763,494

The present invention is a turbo product code decoder decoding multi-dimensional coding schemes. The decoder may be implemented in any digital communication system receiving an encoded stream of data. The decoder is configured for receiving soft decision values. The decoder iteratively decodes the data by generating new soft difference values for each axis-iteration of decoding. These soft difference values represent the change in soft decision values after each axis-iteration. The soft difference values from each axis-iteration are then summed with the original soft decision values in decoding each of the other axis. After any full iteration–i.e. after all axis dimensions have been decoded one full time, the previous difference values for any axis are discarded when that axis is decoded in subsequent iterations. Accordingly, the same information is not continuously fed into the decoder during each subsequent iteration, thereby decreasing the likelihood of error and offering improved decoding. Moreover, using unique nearest neighbor computation logic, the decoder generates valid nearest neighbors more efficiently without requiring the use of a look-up table, thereby reducing the amount of time required to decode. Finally, the decoder utilizes four decoders arranged in parallel along with a unique memory array accessing scheme such that multiple rows or columns may be decoded at the same time, thereby increasing the data throughput time of the decoder.

Method and Apparatus for Selectively Accelerating Network Communications

Patent Number 6,937,560

A method and apparatus for selectively accelerating network communications provides improved operation of network communications through channels with long delays, such as a satellite communications channel. A configuration management mechanism provides a selection of acceleration configuration for particular addresses of devices that may communicate through the communications channels. Acceleration may be bypassed for particular addresses or classes of devices within the network and priorities may be assigned, permitting a cut-off of acceleration when a threshold number of sessions is reached. The method and system may also allow a higher priority class of session to preempt lower priority session by removing resources from the lower priority session and assigning them to the higher priority session. The data rate of the lower priority session is then lowered (due to the absence of acceleration or reduced buffer size) to reduce traffic flow.

Enhanced turbo product code decoder system utilizing a codeword organization method

Patent Number 7,039,846

A method and apparatus for decoding a linear block encoded string of information bits comprising: converting the string into a plurality of codewords. Performing hard and soft decisions on each codeword to generate a hard and soft decision vector. Computing the syndrome and finding the location of the two minimum values by Galois Field Arithmetic. Designating these values LOW1 and LOW2 and xoring with a Nc1, thus generating Nc2. Swapping Nc1 with Nc2 and determining the lowest soft decision value, Min1 and a next lowest value, Min2. The two bit locations creating Min1 are designated as MinA and MinB. MinA being replaced with Min2 minus the value MinA. MinB being replaced with Min2 minus the value at MinB. Generating an output codeword by subtracting Min1 from all other bit locations values and 2’s complementing all soft values with 0 in their location. Creating the new soft value vector. Some embodiments include a system and method that organizes an encoded codeword. The encoded codeword has several codeword bits. The method receives the encoded codeword, assigns multiple codeword bits to at least one memory address in a plurality of memory addresses, and iteratively decodes the received codeword by utilizing the plurality of memory addresses in a predetermined order. The predetermined order is based on a dimension of the received codeword.

Method and Apparatus for Network Signal Aggregation and Bandwidth Reduction

Patent Number 7,072,296

Wireless network demands continually increase as wireless service providers pursue additional service capabilities. In a cellular communication system, leased lines between remote cell sites and the corresponding Mobile Switching Offices (MSOs) remain a major operating cost. Bandwidth reduction by identification and elimination of payload data and control information which need not be fully replicated because it can be deduced from information accessible or previously transmitted allows fewer lines to support the same bandwidth. A wireless access gateway is operable to aggregate such redundant and regenerable data on a backhaul link between a wireless cell site and the corresponding mobile switching office (MSO) to provide low-latency, type specific lossless bandwidth reduction. The wireless access gateway identifies regenerable information and eliminates portions of the data which the device need not transmit because the data is redundant, or accessible or recreatable, at the receiving side. In this manner, the access device allows fewer lines to carry the reduced message traffic by transmitting only the non-recreatable data and eliminating message traffic for regenerable information.

Enhanced turbo product code decoder system

Patent Number 7,085,987

Concatenated turbo product codes for high performance satellite and terrestrial communications

Patent Number 7,107,505

Architecture for enhancing the encoding/decoding of information of a channel. A stream of incoming information bits are arranged into a first array of information bits. The first array of information bits are processed into a first code of bits, which bits form a plurality of first code words having a minimum distance to neighboring error events. Selected bits of the first code are rearranged into a second array of bits by intermittent successive rotations of the selected bits of the first code. A second code is then generated from the second array of bits to increase the minimum distance to the neighboring error events.

Digital Decimation Filter having Finite Impulse Response (FIR) Decimation Stages

Patent Number 7,117,235

A digital decimation filter having Finite Impulse Response (FIR) decimation stages provides improved performance over a Hogenauer decimating filter. The filter comprises multiple integrator stages followed by multiple FIR decimating stages. The zeros of the filter are tunable by adjusting the integer coefficients of the FIR stages providing tunability of the cut-off response, as opposed to the fixed sinc response of the Hogenauer filter. As a result, the number of required stages for a particular steepness is reduced, dramatically reducing the amount of digital circuitry required to implement a particular filter design. The improved filter is especially suitable for use in digital intermediate frequency (IF) stages in receivers, and for code-based applications where selectable decimation rate is desired and a fast multiply is not available.

Soft input-soft output forward error correction decoding for turbo codes

Patent Number 7,117,418

A method of turbo decoding using soft input-soft output information. A vector of data is sampled from a channel of data. The vector of data is then processed to output a final code word of bits. A final reliability vector of reliability values associated with the final code word is generated, such that each bit of the final code word of bits has a corresponding reliability value in the final reliability vector. Corresponding reliability values for one or more bit positions of the final code word are determined by a difference of distance metrics, and corresponding reliability values for one or more bit positions of the final code word are determined utilizing a numerical approximation.

Digital IF Processing Block having Finite Impulse Response (FIR) Decimation Stages

Patent Number 7,213,042

A digital Intermediate Frequency (IF) processing block including a decimation filter having Finite Impulse Response (FIR) decimation stages provides improved performance over a Hogenauer decimating filter. The filter comprises multiple integrator stages followed by multiple FIR decimating stages. The zeros of the filter are tunable by adjusting the integer coefficients of the FIR stages providing tunability of the cut-off response, as opposed to the fixed sinc response of the Hogenauer filter. As a result, the number of required stages for a particular steepness is reduced, dramatically reducing the amount of digital circuitry required to implement a particular filter design. The improved filter is especially suitable for use in digital IF stages in receivers, and for code-based applications where selectable decimation rate is desired and a fast multiply is not available.

Method and System for Modulating and Detecting High Datarate Symbol Communications

Patent Number 7,254,188

A method and system for modulating and detecting high data rate symbol communications provides superior performance in channels having a fixed spectral efficiency. A quadrature amplitude modulation (QAM) constellation and an optimized mapping are employed to encode/detect a communications signal and error correction is provided using high speed forward error correction techniques. A log likelihood detection scheme and/or a novel phase detector may be employed to further enhance performance.

LDPC architecture

Patent Number 7,353,444

The current invention involves a forward error detection system, especially for use with Low Density Parity Check codes. A parallel SISO structure allows the decoder to process multiple parity equations at the same time. There is a new SISO decoder which allows for the updating of the Log-likelihood-ratios in a single operation, as opposed to the two pass traditionally associated with the Tanner Graphs. In the decoder, there is a mapping structure that correctly aligns the stored estimates, the stored differences and the SISOs. There is also the ability to deal with multiple instances of the same data being processed at the same time. This structure manages the updates and the differences in such a manner that all calculations on a single piece of data that are processed in parallel are incorporated correctly in the new updated estimates.

Enhanced turbo product codes

Patent Number 7,356,752

A hyper encoder module encodes a block of data having a plurality of sub-blocks. Each sub-block includes a plurality of systematic block code codewords. A parity sub-block is added to the block. The parity sub-block is a first sub-block rotated by a predetermined number of bits. Each subsequent sub-block in the n-dimensional block is rotated by an appropriate number of bits and bit-wise XORed. An encoder method and apparatus which includes the hyper encoder module receives the block of data. A row of the block is immediately output and encoded by a first module according to a first encoding scheme. A column is encoded by a second module according to a second encoding scheme. A second set of encoded data is generated, iteratively updated and output by the second module. The hyper encoder module hyper-diagonally encodes the information bits as described above and then output.

System for Optimization of Database Replication/Synchronization

Patent Number 7,359,926

A system for optimization of database replication/synchronization includes a first computer-based device having software thereon for obtaining a state of condition a database object and associating a unique identifier with such database object, for altering form of the data and associating another unique identifier with such altered database object, and for determining the database object using the unique identifiers. The system can receive a replication request for updating data from a second computer for a database object on the second computer wherein the request contains a unique identifier comparatively equating to one of the identifiers on the first computer and sends either an instruction to second computer to perform a like alteration on the data or to send the changes to the database object.

SISO decoder

Patent Number 7,415,659

The current invention involves a forward error detection system, especially for use with Low Density Parity Check codes. A parallel SISO structure allows the decoder to process multiple parity equations at the same time. There is a new SISO decoder which allows for the updating of the Log-likelihood-ratio’s in a single operation, as opposed to the two pass traditionally associated with the Tanner Graph’s. In the decoder, there is a mapping structure that correctly aligns the stored estimates, the stored differences and the SISO’s. There is also the ability to deal with multiple instances of the same data being processed at the same time. This structure manages the updates and the differences in such a manner that all calculations on a single piece of data that are processed in parallel are incorporated correctly in the new updated estimates.

Enhanced turbo product code decoder system

Patent Number 7,421,638

Method and System Capable of Performing a Data Stream over Multiple TCP Connections or Concurrent Interleave of Multiple Data Streams over Multiple TCP Connections

Patent Number 7,543,072

A system for performing concurrent interleaves of multiple data streams over multiple TCP/IP connections includes a computer having data stream optimizing software for identifying the need of data stream exchange and initiating TCP/IP software to enable multiple TCP/IP connections, wherein data stream optimizing software is capable of uniquely splitting the obtained data, monitoring each established TCP/IP connection for availability of data transmission and transmitting over at least one of the TCP/IP connections based upon its availability the split data to another computer having data stream optimizing software thereon having the ability to assemble the split data received in a manner to be readily used.

Generating dynamic huffman codes

Patent Number 7,609,182

Huffman trees may be rapidly and effectively created by sorting a plurality of nodes by weight in an insertion sorter stack, popping the two lowest weighted nodes from the insertion sorter stack, forming a branch node from the popped entries, and placing the branch node into the insertion sorter.

Method and Apparatus for Low Latency Signal Aggregation and Bandwidth Reduction

Patent Number 7,720,094

System for Selectively and Automatically Compressing and Decompressing Data and Enabling Compressed Data to be Rendered in a Psuedo-Native Form

Patent Number 7,743,102

A system for selectively and automatically compressing and decompressing data in a manner such that the data file can be rendered in a pseudo-native form and such that a rendering application program can be invoked by the system includes a first computer-based device having software thereon for determining whether a data file is one of a native uncompressed form and compressed form upon one of attaching, detaching, receiving, rendering and accessing the data file. Software compresses the native uncompressed form of the data into an attachment, and software for enhancingly renders the attachment to a viewer in a pseudo-native form, wherein the attachment remains compressed and is rendered to appear as being in a native-uncompressed form.

Decompressing dynamic huffman coded bit streams

Patent Number 7,764,205

A method and system for decompressing dynamic Huffman coded bit streams is disclosed.

Method and system for increasing data access in a secure socket layer network environment

Patent Number 7,890,751

A system for increasing data access in a secure socket layer network environment includes a web server computer having SSL acceleration server software (SSLAS) and a client computer communicatively linked to the web server computer having SSL acceleration client software operably associated with the client computer which communicates with the SSLAS software to receive a copy of a pseudo CA certificate and a public key from the SSLAS software and present the pseudo CA certificate to web browser software on the client computer for validation thereof.

Timing recovery scheme for satellite backhaul link

Patent Number 7,929,907

A remote satellite modem, in conjunction with a mediation device configuration propagates frames over a cellular backhaul link so as to preserve PRC traceability by receiving a frame based signal, in which the frame based signal conforms to a hub timing signal operable to demarcate frames in the frame based signal, and identifies a start of frame in the received frame based signal, such that the start of frame is independent of the symbol timing of the hub timing signal. In response to the start of frame, the modem generates a timing packet corresponding to a remote timing signal, and forwards the timing packet and the frame based signal, in which the timing packet is for decoding the frame based signal corresponding to the hub timing signal using the remote timing signal.

Signal filtering system and related methods

Patent Number 7,991,373

A signal filtering system for a frequency reuse system. A first implementation may include a downlink baseband signal, coupled to a downlink bandwidth filter, including a composite received signal including at least an interfering signal and a signal of interest, each having a composite bandwidth, a first bandwidth, and a second bandwidth, respectively. An uplink baseband signal may be included, coupled to an uplink bandwidth filter, having a replica of the interfering signal corresponding with the interfering signal and having an interference bandwidth. A baseband processing module may be coupled with the downlink bandwidth filter and the uplink bandwidth filter and may be configured to cancel the interfering signal from the composite received signal using the replica of the interfering signal. The downlink bandwidth filter may be configured to reduce the composite bandwidth and the uplink bandwidth filter may be configured to reduce the interference bandwidth.

Redundancy system for a telecommunication system and related methods

Patent Number 8,022,781

A redundancy system for a co-channel telecommunication system and related methods. Implementations of the redundancy system may include at least a first modulator and a second modulator having a symbol mapper coupled to a parallel bit signal. The symbol mapper may be configured to route each of a plurality of parallel bits received through the parallel bit signal to a plurality of significant bit signals. In a first implementation, a plurality of significant bit signal multiplexers may be used to switch the plurality of parallel bit signals to allow the first and second modulators to operate in either a redundant or operating mode. In a second implementation, a premapped symbol (PMSI) encoder and a PMSI decoder may be used to transmit the plurality of significant bit signals across an interface bus as a real dual-data rate (DDR) signal and an imaginary DDR signal.

Content addressable memories and state machines for performing three-byte matches and for providing error protection

Patent Number 8,028,125

A method and system for detecting matching strings in a string of characters utilizing content addressable memory is disclosed.

Content-addressable memories and state machines for performing three-byte matches and secondary matches, and for providing error protection

Patent Number 8,046,532

A method and system for detecting matching strings in a string of characters utilizing content addressable memory using primary and secondary matches is disclosed.

Adaptive refresh rate for header compression over long propagation channels and related methods

Patent Number 8,060,646

An adaptive telecommunications packet transmission system. Implementations may include a compression engine configured to compress a header of at least one uncompressed packet and to send at least one compressed packet corresponding to the at least one uncompressed packet across a communication channel coupled to the compression engine. A refresh rate calculator may be included that is configured to receive at least one error and at least one success from a decompression engine and calculate an adaptive refresh rate based on the at least one error or the at least one success. The refresh rate calculator may be configured to communicate an adaptive refresh rate to the compression engine. The compression engine may be configured to transmit at least one uncompressed packet across the communication channel according to the adaptive refresh rate received from the refresh rate calculator.

Assigning codes to and repairing Huffman trees

Patent Number 8,106,797

A method for assigning codes to Huffman trees and repairing invalid Huffman trees is disclosed using a calculated delta and moving nodes within the Huffman tree by adjusting their encode register entries.

Burst processing modem

Patent Number 8,107,515

A burst processing modem. Implementations may include a receive side including a channelizer adapted to process a plurality of channels and write a plurality of frames to a receive RAM array. A receive frame state machine may be adapted to generate a timing signal using a burst time plan for the plurality of frames. A demodulator may be coupled with the receive RAM array and adapted to read from the receive RAM array only the one or more bursts from the plurality of frames indicated by the timing signal. A transmit side may include a modulator coupled with a transmit frame state machine, with a transmit RAM array, and a combiner bank. The combiner bank may read the modulated plurality of channels from the transmit RAM array and assemble a plurality of frames using a timing signal generated from a burst time plan by the transmit frame state machine.

Data packet encapsulation methods

Patent Number 8,108,546

A data encapsulation system and related methods. Implementations may include: forming at least one frame having a data payload, a data sequence, and one or more control bytes; evaluating data to be stored in the data payload and setting a value of the one or more control bytes, where the value of the one or more control bytes may be equal to: a first control byte value where one or more values of the data correspond with the first control byte value; a second control byte value indicating a size of the data; or a third control byte value where one or more values of the data continue beyond the frame. The value of each one of the one or more control bytes for each of the at least one frames may be equal to either the first, second, or third control byte values.

Other Third Party Patents

Adaptive canceller for frequency reuse systems

Patent Number 6,859,641

An adaptive interference canceller for canceling an interfering signal corresponding to a delayed, frequency translated, amplitude and phase offset version of a transmitted signal contained in a composite received signal relayed through a relay system such as a satellite transponder. The canceller digitally downconverts the received signal and a local replica of the transmitted signal from IF to baseband, applies a variable delay and frequency compensation to the replica as a coarse delay and frequency correction, and tracks fine delay, amplitude and phase differences using an adaptive finite impulse response filter to generate a cancellation signal corresponding to the delayed and frequency shifted version. A minimum output power process produces an error signal that drives the variable delay and adaptive filter to minimize the power in the signal of interest to maximize cancellation of the interfering signal.

Frequency analysis

Patent Number 6,907,083

An apparatus for frequency content separating an input signal is disclosed. The apparatus comprises a plurality of frequency splitting stages, each stage including one or more up-converter and down-converter pairs. An up-converter and down-converter pair serves (i) to receive a complex input signal representing an input bandwidth and (ii) to output a first complex output signal representing an upper portion of the input bandwidth and a second complex output signal representing a lower portion of the input bandwidth. The upper portion and the lower portion being contiguous and together representing the input bandwidth portion.

Adaptive canceller for frequency reuse systems

Patent Number 7,228,104